Satellite positioning apparatus

ABSTRACT

A new and improved apparatus for determining the position of a vehicle or vessel on the earth&#39;&#39;s surface by processing signals sent from a satellite, based on the doppler shift in frequency of the signals so sent, and the orbit description data encoded in the signals.

Rigdon et a].

1451 Sept. 16, 1975 41 SATELLITE POSITIONING APPARATUS 3.191,!76 6/1965Guicr 235/150271 x 3,242,467 3/1966 Lamy 340/1725 1751 memory James WR'gdom Sabum 3.471356 10/1969 Laughlin. Jr. et a1. 343/100 ST x LeRoyGrab", of "0118mm 3,680,124 7/1972 Stonc 612111 343/100 ST x 3,702,47711/1972 Brown 343/112 C [73] Assignee: Seiscom Delta Inc.

[22] Filed: Apr. 20, 1973 Primary Examiner-Joseph F. Ruggiero pp No:352,953 Attorney, Agent, or Firm-Pravel & Wilson [52] US. CL...235/l50.27; 340/172.5; 343/100 ST;

343/112c [57] ABSTRACT [51] Int. Cl. G061 /50; G015 5/00 A new andimproved apparatus for determining the [58] Field of Search...235/150.27, 150.271, 150.26, 1

posltlon of a vehlcle or vessel on the earth s surface by 235/1502,150.24; 343/100 ST, 100 C, D1G l f v d th 244/77 SS 340/172 5 processmgslgnas sent rom a sa e lte, ass on e doppler shlfi 1n frequency of theslgnals so sent and References Cited the orbit description data encodedin the signals UNITED STATES PATENTS 10 Claims, 10 Drawing Figures3,172.108 3/1965 McClure 343/100 ST /1 0701 TAPE 7 FAA/4 R5405? 6' 0/ 7/070? 1" awn/1y x JWTEZZ/TE 1N7? 3/6/1641 M 0 RE Cf/VE AEVBOAADI PATENTEDSEP I 81975 SHEET 1 or 5 PATENTED SEP 1 6 I975 SHIT 3 I]? PATENIEB SEP1B 5975 sum u 0F 5 SATELLITE POSITIONING APPARATUS BACKGROUND OF THEINVENTION l. Field of the Invention The present invention relates todetermining the position of vehicles or vessels on the surface of theearth.

2. Description of Prior Art The United States Navy Navigation SatelliteSystem (NNSSJ using multiple orbiting Transit Satellites to send data inthe form of doppler shift signals and orbit definition data at repeatedtime intervals. as disclosed in US Pat. Nos. 3.l91,l76 and 3.172.208 wasmade available for commercial use in I967.

Since this Navy Navigation Satellite System was developed primarily formilitary use, it was considerably more sophisticated and complex. andthus more expensive. than necessary for commercial purposes, such asnavigation of seismic exploration vessels. fishing craft. and othermarine transportation vessels. Accordingly, this system and similarsystems using similar design techniques have not enjoyed widespread usein nonmilitary navigation systems.

SUMMARY OF INVENTION Briefly. the present invention provides a new andimproved apparatus for determining the position of a vessel or vehicleon the earth from the doppler shift in fre quency of the signal sentfrom a satellite and from the orbit definition or description data sentas the signal from the satellite. The satellite positioning apparatus ofthe present invention includes a receiver for the signal sent from thesatellite which demodulates the frequency of the satellite signal todetermine the doppler shift therein and decodes the orbit definitiondata sent by the satellite signal. a computer for processing the dopplershift and orbit definition data to determine the location and positionof the vehicle. an interfere circuit including a doppler counter forproviding the doppler shift and orbit definition data to the computerfrom the receiver, and a display for indicating the location of thevehicle determined by the computer.

The present invention includes several new and improved featurespermitting a satellite positioning apparatus of reduced complexity andcost. By way of example. doppler shift information. in the form ofdoppler shift count, and the satellite orbit description data are timedivision multiplexed in a data multiplexer before being processed in thecomputer, permitting a small computer to be used on the time-sharedbasis. Further. since each of the Transit Satellites sends signals atrepeated two minute intervals. an interrupt circuit notifies thecomputer of receipt of a new message so that the computer can call forthe new message. A message reject circuit is also provided. whichsuppresses output of orbit definition data to the computer until thecomputer requests it. preventing new incoming data from interfering withpositioning computations of the computer at undesired times.Additionally. an error detection circuit is provided in order to preventerrors in data received from the satellite from affecting positioncalculations.

The present invention further provides a new and im proved controlkeyboard for prompt and accurate entry of data and requests thereforinto the computer. Additionally, when it is desired to use a doublechannel satellite positioning apparatus receiving both frequencychannels of signals sent from the Transit Satellite. the

present apparatus may be readily adapted for such double channel use.without requiring redesign and extensive modification of the existingsingle channel system. It is an object of the present invention toprovide a new and improved satellite positioning apparatus.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. I is a schematic diagram of theapparatus of the present invention;

FIG. 2 is a schematic electrical circuit diagram of the control panel ofthe apparatus of the present invention;

FIG. 3 is an elevation view of the control panel and display of theapparatus of the present invention;

FIG. 4 is an elevation view of the control keyboard for entry by anoperator of data and requests therefor into the apparatus of the presentinvention;

FIG. Sis a schematic electrical circuit diagram of the display sectionof the apparatus of the present inven' tion;

FIG. 6 is a schematic electrical circuit diagram of the control keyboardsection of the apparatus of the pres ent invention;

FIGS. 7A, 7B and 7C are schematic electrical circuit diagrams of thereceiver section ofthe apparatus of the present invention; and

FIG. 8 is a schematic electrical circuit diagram of the interfacecircuit of the apparatus of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT In the drawings. the letter Adesignates generally the apparatus of the present invention forprocessing data. sent from a satellite in the form of a frequency signalcontaining phase modulated pulse doublets of orbit definition data todetermine a position of a vehicle on the earth. It should be understoodthat the vehicle with which the apparatus A is used may be a marine orwaterborn vessel or vehicle. as well as a land vehicle or an aircraft.if desired.

The apparatus A includes a receiver R (FIGS. I, 7A. 7B and 7C) forreceiving the fixed frequency signal containing the phase modulatedpulse doublets of orbit definition data sent from the orbitingsatellite. The receiver R, in a manner to be set forth below,demodulates the fixed frequency signal to determine the doppler shift inthe frequency of the signal sent from the satellite and decodes thephase modulated pulse dou blets of orbit definition data in the signal.The receiver R provides the doppler shift in the frequency and the orbitdefinition data to an interface circuit I (FIGS. 1 and 8) which includesa doppler counter to count the doppler shift in frequency of the signalfrom the satellite. The interface circuit I provides the doppler shiftcount and the orbit definition data to a computer C (FIG. I).

The computer C receives an operation controlling computer program from atape ready T in order to control the operation of the computer C toprocess the data received from the interface circuit I and determine theposition of the vehicle on the earth.

A display D(FIGS.1, 3 and 5) receives data from the computer C and formsan output indication of the location of the vehicle determined by thecomputer C. A control keyboard K (FIGS. 1, 4 and 6) permits an oper atorof the apparatus A to enter data and requests for data and computationsinto the computer C through display D. The display D further provides anindication to the operator of the particular data. requests for data orcomputations requested by the operator using the control keyboard K.

The apparatus A further includes a control panel P (FIGS. 1 3) havingthe display D mounted therein (FIG. 3) and further providing indicationsof the operational condition of the apparatus A, the doppler fre quencyshift of the signal. as well as permitting manual control of certainoperations of the apparatus A, as will be set forth below.

RECEIVER R The receiver R of the apparatus A receives the signal fromthe satellite and determines the doppler shift in the frequency of thesignal sent from the satellite as well as decodes the orbit definitiondata from the phase modulated pulse doublets in the signal sent from thesatellite. as has been set forth above. Considering the receiver R morein detail (FIGS. 7A 7C). a receiving antenna N thereof receives thefixed frequency signal from the satellite and provides such signal to aninter mediate frequency circuit F which demodulates the fixed frequencysignal received by the antenna N and provides such signal to a phasedetector O which determines the phase of the demodulated signal from theintermediate frequency circuit F. A phase lock loop cir' cuit M receivesan output signal from the phase detector Q to regulate the frequency ofthe intermediate frequency circuit F.

A doppler demodulator X responds to the output of the phase lock loop Mto determine the doppler shift in the frequency ofthe signal sent fromthe satellite and received by the antenna N. A local oscillator forms areference frequency signal for use in receiver circuit R and furnishesthis signal to a synthesizer circuit S which forms demodulatingfrequency signals for the intermediate frequency circuit F. the phasedetector 0 and the doppler demodulator X. A bit phase detector circuit Breceives an output signal from the phase detector Q and determines thephase of the orbit definition data pulse doublets received from thesatellite. A bit rate phase lock loop circuit L responds to the outputfrom the bit phase detector B and controls the phase of the orbitdefinition data pulse doublets.

A data decoder circuit y receives an output signal from the phasedetector circuit 0 and decodes the orbit definition data from the phasemodulated pulse doublets. providing such orbit definition data to theinterface circuit I for provision thereby to the computer C.

The receiver R further includes a message synchronization counter Zwhich detects the synchronization pattern code of one logic 0,twenty-three consecutive logic 1 pulse doublets and a final logic 0pulse doublet. The synchronization pattern code is well known in the artand the decoding thereof is by conventional digital logic decodingtechniques. The message synchronization counter Z detects thissynchronization pattern code and indicates receipt of such code to thecomputer C through the interface circuit l.

The antenna N (FIG. 7A) senses the 400 megahertz fixed frequency signalsent from the orbiting Transit Satellite and provides such signal to aconventional pre amplifier 10 tuned to this center frequency, since theactual frequency received depends on the doppler shift due to satellitemovement. As is known, it not infrequcntly occurs that more than oneorbiting satellite is within radio range. As will be set forth below,the appa ratus A provides the user thereof with a choice of theparticular satellite whose signals are to be processed.

The amplifier 10 provides the doppler containing frequency signalreceived by the antenna N to a first lF stage 12 of the intermediatefrequency circuit F. A mixer 14 ofthe first IF stage receives thesatellite signal from the preamplifier l0 and further receives a 360megahertz demodulating signal over a conductor 16 which is formed in thesynthesizer circuit S in a manner to be set forth below.

A filter l8 tuned to 40 megahertz, the difference between the 400megahertz and the 360 megahertz signals fed to the mixer 14, receivesthe output of the mixer 14 and provides such output containing the 40megahertz signal less satellite doppler shift to a gain controlledamplifier 20. The amplifier 20 provides the amplified 1F signal to asecond lF stage 22 of the intermediate frequency circuit Fv A mixer 24receives the output signal from the amplifier 20 of the first IF stage12 and further receives a 55 megahertz signal, less doppler shift, fromthe phase lock loop circuit M over a conductor 26, formed in a manner tobe set forth below.

A filter 28 tuned to the fifteen megahertz difference in frequencybetween the two input signals to the mixer 24 receives the output of themixer 24 and furnishes such output to a gain controlled amplifier 30which provides the output signal from the second IF stage 22 of theintermediate frequency circuit F to a first mixer 32 and a second mixer34 of the phase detector circuit Q.

The first mixer 32 of the phase detector Q further receives a fifteenmegahertz demodulating frequency signal from the synthesizer S over aconductor 36. The second mixer 34 of the phase circuit 0 receives a 15megahertz signal, in phase quadrature to the signal present on theconductor 36, as will be set forth below, from the synthesizer S over aconductor 38.

Accordingly, when the input signal to the mixer 32 from the amplifier 30of the intermediate frequency circuit F is substantially in phase withthe signal present on the conductor 36, the mixer 32 provides an outputsignal over a conductor 40 of measurable amplitude which is furnished toa gain controlled amplifier 42 which provides a signal over conductors44 and 46 to the gain control input terminals of the gain controlledamplifiers 20 and 30 in order to limit the gain of the two [F stages ofthe intermediate frequency circuit F.

When the signal from the mixer 32 on the conductor 40 is of measurableamplitude due to the phase alignment of the two inputs to the mixer 32,the mixer 34 forms an output signal of substantially zero DC volts. dueto the phase quadrature of the signals on the conductors 36 and 38. Theoutput from the mixer 34 is provided over a conductor 50 to the phaselock loop means M.

The phase lock loop means M includes a filter/amplifier 52 whichreceives the output signal from the mixer 34 and forms an output voltagewhich is furnished to a voltage controlled crystal oscillator (VCXO) 54in order to control the frequency thereof. The VCXO 54 provides anoutput signal which varies about a center frequency over a fraction ofthe normal doppler shift range in accordance with the output voltagefrom amplifier 52 so that this center frequency when multiplied infrequency by a "TIMES 4" frequcncy multiplier circuit 56 forms the 55magahertz signal less doppler shift furnished to the mixer 24 of theintermediate frequency circuit F. A conductor 58 furnishes the output ofthe phase lock loop circuit M to the doppler demodulator X (FIG. 7B).

The synthesizer 5 receives a stable frequency signal of 5 megahertz fromthe local oscillator O and synthesizes a [5 megahertz demodulatingfrequency in a TIMES 3" frequency multiplier 60 which is provided. ashas been set forth, over the conductors 36 and 38 in phase quadrature tothe phase detector Q, A TlMES 24" frequency multiplier 62 of thesynthesizer S further receives the i5 megahertz signal formed in thefrequency multiplier 60 and forms therefrom a 360 megahertz demodulatingsignal which is provided over the conductor l6 to the mixer 14 in thefirst lF stage 12 of the intermediate frequency circuit F in order todemodulate the incoming 400 megahertz signal from the satellite.

A "TIMES ll" frequency multiplier 64 receives the 5 megahertz outputsignal from the oscillator 0, forming therefrom a 55 megahertz signalwhich is fed to a doppler demodulator mixer 66 in the dopplerdemodulator X. The doppler demodulator mixer 66 further receives the 55megahertz less doppler shift signal from the phase lock loop M presenton the conductor 58, through a buffer amplifier 68.

The doppler demodulator mixer 66 accordingly receives and responds tothe output of the phase lock loop circuit M and the demodulatingfrequency formed in the multiplier 64 forming an output signalindicating the doppler shift in the frequency of the signal sent fromthe satellite which is provided through a buffer amplifier 70 over aconductor 72 to the interface circuit 1 (FIG. 8).

The bit phase detector B (FIG. 7) receives at an input active filter 74the gradually fluctuating output from the mixer 32 present on theconductor 40. The filter 74 passes the 101 hertz train of phasemodulated doublets of orbit data definition, which are provided througha buffer amplifier 76 to a D flip-flop 78 at a T, or trigger input. 78::thereof. A D input 78b of the flip-flop 78 receives a comparison signalfrom the data decoder circuit Y, formed in a manner to be set forthbelow. so that unless the D input terminal 78!) is receiving a logic Iwhen activated by at logic I at the trigger input 78a. a Q output 78c ofthe flip-flop 78 remains at a logic G level indicating that the datapulse doublets are not in phase An output conductor 80 provides thissynchronization signal from the bit phase detector B to the interfacecircuit while an inverter 82 provides an inverted version of the signalpresent on the terminal 80 over an output conductor 84 to the interfacecircuit 1. The frequency of the signal furnished to the trigger input78a ofthe flip-flop is substantially equal that present on the D inputterminal 78b of the flip-flop 78, since as will be set forth below thesignal presented to the terminal 78b is at the hertz data processingrate. Thus. the presence of a logic I on the output conductor 80 fromthe bit phase detector 8 indicates that the bit phase detec tor B hasdetermined that the phase of the orbit definition data pulse doublets isin synchronism with the data processing frequency formed in the datadecoder Y A digital phase detector 86 receives an input signal from thebuffer amplifier 76 representing the pulse doublet portion of the signalformed in the mixer 32 and provided to the bit phase detector B over thecoductor 40. The digital phase detector 86 further rcceivcs an inputsignal representing the desired phase and frequency of the orbitdefinition data pulse dou blets received from the satellite over aconductor 88 from the data decoder circuit Y. The digital phase detector 86 is a conventional digital phase detector, forming a logic 1signal at an output terminal 86a and furnishing same over an outputconductor 90 to a bit rate phase lock loop circuit L when the inputsignals to the phase detector 86 are in a first phase relationship suchas the phase of the signal present on the conductor 88 being in a phaseleading relation The phase detector 86 forms a second output signal atan output terminal 8619 which is a logic 1 level when the input signalsare in an opposite phase relationship. furnishing this signal over aconductor 92 to the bit rate phase lock loop circuit L.

An operational amplifier 94 ofthe bit rate phase lock loop circuit Lreceives the input signals present on the conductors 90 and 92 and formsan output signal whose polarity indicates which ofthe input signals isin a logic I level. The output signal from the amplifier 94 is furnishedthrough a filter 96 to a voltage controlled crystal oscillator (VCXO) 98which forms an output fre quency of approximately [.024 megahertzdependent on the voltage presented thereto by the filter 96 and providessuch output frequency signal to a frequency divider 100 which reducesthe frequency of the oscilla tor 98 by a factor of 32, providing thisreduced frequency signal over a conductor 102 to the data decodercircuit Y,

Considering the data decoder circuit Y of the receiver R more in detail.a frequency divider circuit 104 receives the 32 kilohertz signal fromthe frequency divider 100 in the bit phase lock loop circuit L and formstherefrom requisite frequency signals by frequency division inconventional digital logic circuits to form a one-hundred one outputsignal over an output conductor 106, an 800 hertz output signal over anoutput conductor 108, a 200 hertz output over an output conductor and a400 hertz output signal over an output conductor 112. The 100 on hertzsignal present on the conductor 106 and the 800 hertz signal present onthe conductor [08 are combined in an AND gate 114 and provided over aconductor 116 to the D input 78b in the bit phase detector circuit 8, todetect synchronization of the pulse doublets as has been set forth. Alsoas has been set forth. the lOl hertz signal present on the conductor 106is provided over the conductor 88 to the digital phase detector 86 inthe bit phase detector circuit B.

A data timing circuit 122 of the data decode circuit Y receives the lOlhertz signal on the conductor 106, the 800 hertz signal on the conductor[08, the 200 hertz signal on the conductor 110 and the 400 hertz signalon the conductor [12. The circuit 122 combines these pulses inconventional gates to form a data readin or strobe pulse on a conductor126 in synchronism with the incoming phase doublets present on the con'ductor 50 provided to a D input 124m of a data read-in flip-flop 124 inthe data decode circuit Y. The timing or strobe pulse formed in the datatiming circuit 122 is provided over the conductor 126 to a T input [24bof the flip-flop 124. The circuit [22 further divides the lOl hertzfrequency pulses received by a factor of two in a conventional frequencydivider to form a St) hertz bit sync or data rate signal on an outputconductor 132.

Accordingly, the flip-flop 124 presents the logic state of the incomingphase doublets received at Q and 6 output terminals 124(' and 124d.respectively. thereof in response to the clock pulse on the conductor126. The signal present at the Q output 124C of the flip-flop 124 isread into the flip-flop 120 at a D input terminal [20!) thereof by theclock pulse provided to the input terminal 1200 over the conductor 118in the manner set forth above. Thus, when a logic 1 is present at theoutput terminal 124c during a preceding clock cycle of the signalpresent on the conductor 118. a Q output terminal 1201- of the flip-flop120 assumes a logic I state. Conversely. when a logic signal is presentat the terminal 124e, a 6 output terminal 120d of the flip-flop 120 isdriven to a logic l level during the next clock cyclcv As is known. thesatellite orbit definition data signals are in the form of phasemodulated pulse doublets composed of two half-bits transmitted twice ata bit rate of 50 cycles per second. with the second half-bit beingtransmitted being in reverse polarity to the first half-bit. The phaseof the doppler signal is advanced and then retarded to represent binaryl during a half-bit and retarded and then advanced for the reversepolarity. Conversely. the phase of the doppler signal is retarded andthen advanced to represent binary 0 during the first half-bit andadvanced and then retarded during the second half-bit.

A decoding NAND gate 128 is connected to receive the output of the 6terminal 120d of the flip-flop 120 and the Q terminal 124( oftheflipflop 124, so that the presence of an advanced phase during the firsthalf-bit of the phase modulated pulse doublet, recognized and decoded inthe flip-flop 120 as a logic l at the Q output terminal lc and a logic 0at the 0 output terminal 120d. and a retarded phase during the secondhalt bit. interpreted by the flip-flop 124 as a logic 0 at the outputterminal 124e, is decoded by the NAND gate 128 to be a logic I level atthe output terminal of such gate. This logic I output is transferred toa D input terminal 130a of a flip-flop 130 by the 50 hertz bit syncsignal formed in the data timing circuit and provided to a trigger input130!) of the flip-flop 130 over the conductor 132. The frequency of thebit sync signal present on the conductor 132 is one-half that of theoccurrence of the doublets in the half-bits at 101 hertz of the orbitdata definition signal.

A 0 output terminal 1301' of the flip-flop 130 presents a logic 1 outputsignal whenever the data content of the orbit data definition as encodedin the phase modulated doublets and decoded by the decoding gate [28indicate such data to be a logic 1. Conversely. a 6 output terminal 130dof the flip-flop 130 presents a logic I output signal when the decodinggate 128 and decoding flip-flops 124 and 120 determine the data contentof the doublet currently being decoded to be a logic 0. An outputconductor 132 provides the data from the output terminal lc to theinterface circuit 1. while an output conductor 134 provides the outputfrom the terminal 130d to the interface circuit I.

An output conductor 136 provides the 50 hertz bit synchronization signalto the interface circuit 1.

As has been set forth. the two half-bits in each bit of data sent fromthe satellites are opposite in polarity from each other. Accordingly.consecutive appearance of like polarities. interpreted by the decodingflip-flops 124 and to be either consecutive logic 1 or consec utivelogic 0. are erroneous data. and a data error detection circuit 140detects such erroneous data and prevents such data from being furnishedto the interface circuit 1.

A first AND gate 142 is connected to the 0 terminals 120C and 1241' andsenses the consecutive occurrence oftwo high half-bits in the data.forming a logic 1 sig nal to indicate same. A second AND gate 144 is connected to the( output terminals 120d and 124d. forming a logic l outputsignal in response to the presence of two consecutive lows" in half-bitsof the orbit definition data.

Presence of a logic I at the output of either of the AND gates 142 and144 drives the output of a NOR gate 146 to a logic 0 level which isfurnished to a digital counter 148 at a clear input terminal 148athereof. The digital counter 148 receives the data rate signals from theconductor 132 at a clock input terminal 148 over an input conductor 150.The counter 148 counts a predetermined number of valid data cyclesbefore permitting such data to be transmitted to the interface 1 andtherefrom to the computer C.

As has been set forth. the error detection circuit 140 furnishes a logic0 signal to the clear input terminal 148a of the counter 148. Presenceof this logic 0 lever drives a Q output terminal 1481 of the counter 148to logic 0. preventing the counter 148 from counting so long as theerror detection circuit 140 is receiving and detecting errors in thedata bits from the satellite.

Conversely. when valid data. as verified by the error detection circuit140, are present the counter 148, after eight data bit intervals. causesthe output terminal [48c to go to a logic l level. energizing a clockinput terminal 1520 of a message reject flip-flop 152. A D inputterminal 152b of the flip-flop 152 is connected to a positive or logic Isignal level so that receipt of a positive going signal at the clockinput terminal 152a drives a 0 output terminal 152(- of the flip-flop152 to a logic l level.

A conductor 154 electrically connects the 0 output terminal l52c of theflip-flop 152 to a preset control terminal a of the flip-flop 130. Thepreset control terminal l30e of the flip-flop 130 does not respond tothis logic 1 level, permitting such flip-flop to pass data to thecomputer C.

The present control terminal 1302 of the flip-flop 130 responds to alogic 0 at the output terminal thereof and sets the Q output terminal[30c of the flip-flop 130 to logic I and the?) output terminal 1311b ofthe flip-flop 130 to logic 0. maintaining such output terminals in suchlogic states regardless of the presence of input data for the durationof the logic 0 at the preset input terminal 130e.

In this manner. receipt of a message reject signal. formed in theinterface circuit l in a manner to be set forth below. by the flip-flop152 at a clear input terminal 152d thereof from an input conductor 156causes the 0 output terminal of the flip-flop 152 to be driven to alogic 0 state. suppressing output signals from the data decoder circuitY in response to a message reject signal from the interface circuit 1and the computer C.

As has been set forth. the message sync counter Z of the receivercircuit R responds to the alert codes sent by the satellite in the formof a logic 0. followed by 23 logic I signals and a subsequent logic 0.presented thereto over an input conductor 158 from the data decoder Y.The message sync counter 7. indicates receipt of the alert code overoutput conductors I60 and I62 to the control panel P and to theinterface circuit I. respectively.

INTERFACE CIRCUIT The interface circuit I provides an interconnectionbetween the receiver R and the computer C. as has been set forth.permitting the computer to process the doppler shift and orbitdefinition data to determine the location of the vehicle on the earth.Considering the interface circuit I more in detail. a frequency divider164 receives the local reference signal from the oscillator over theconductor 36. The frequency divider 64 is a conventional digital logicfrequency divider dividing the megahertz logic reference signal down toa It) cycles per second rate which is furnished over a conductor I66 toa clock interrupt circuit 168. The clock interrupt circuit 168 forms anoutput pulse when encrgized every 100 milliseconds by the frequencydivider I64 over the conductor 166. thereby providing a local referencefrequency for the internal clock within the computer C. which isrepetitively called for at this time interval from the circuit I68 bythe computer C. so long as the computer C is operating satisfactorily.

An interrupt circuit I70 responds to the output of the bit rate signalinverted in the inverter 82 of the hit phase detector B (FIG. 7C) andfurnished over the conductor 84 to cnergi7c the interrupt circuit I70,causing same to form a pulse provided over a conductor 172 to thecomputer C indicating that the orbit definition data hits in thesatellite signal are synchronized and ready for processing by thecomputer C. A doppler counter [74 receives the doppler frequency signalfrom the conductor 72 and counts the nutnber of pulses in such dopplerfrequency which occur during the time interval between successive pulsesfrom the bit phase detector B furnished over the conductor 80. Since thedoppler counter I74 accordingly must count only for the dura tion oftime between the St) hertz pulses present on the conductor 80, a muchsmaller doppler counter is required. permitting simplification andreduction of the complexity of the doppler counter as contrasted to theprior art counters requiring large capacity counters with overflowcapacity due to the long time duration between read-outs.

A data multiplexer [76 receives the output from the doppler counter I74as well as the decoded data from the data decoder Y. The datamultiplexer I76 is a conventional time division multiplexer whichresponds to a control signal over a conductor I78 from the com puter Cin response to the signal furnished by the interface circuit over theconductor I72. causing the data multiplexer I76 to multiplex the decodedorbit description data and doppler count from the doppler counter I74for processing by the computer C. A conductor 18" in the interfacecircuit I transmits to the computer C the output of the bit phasedetector B present on the conductor I62. indicating that the hits beingreceived are in synchronism and that processing of the data cancontinue. A message reject circuit 182 of the interface circuit lincludes an RS flip-flop I84 responding to a start signal from thecomputer C at an S input I841: thereof to drive a 0 output terminalI84!) to a logic I level Conversely. the llip'flop I84 responds t o astop ignal at an R input terminal 184v. driving a 0 output terminal I84!to a logic I level and cnergi/ing a first input of an AND gate I86. Asecond input of the AND gate 186 is electrically connected to theconductor so that when the bit phase detector B indicates with a logic Ioutput signal on such conductor that the rc ceived satellite signals arein synehromsm with the local hits in the bit phase lock loop I.. acondition which would normally cause the computer C to accept the dataregardless ofthc current process being performed. the computer C isprovided with an alternative. The computer C cart if the programcontrolling same so detcrmincs. override and ignore the notificationthat incoming data is awaiting processing. permitting the computer C tocontinue with the present operation by providing a stop signal to thellip-flop I84. driving the output of the AND gate I86 to the logic (Ilevel which is provided over the conductor I56 to the message re jectflip-flop 152 which. as has been set forth above. suppresses outputsignals from the data decoder Y in response to the message reject signalfrom the message reject circuit I82 in response to the computer C.

COMPUTER The computer C of the present invention may be any conventionalgeneral purpose digital data processing machine such as. in thepreferred embodiment. a NOVA 1200 computer sold by Data GeneralCorporation of Southboro. Mass. Suitable methods for controlling theoperation of the computer C to determine the position of the vehicle onthe earth are conventional and known in the art and are set forth. forexam ple in U.Sv Pat. Nos. 3.|72,l()8 and 3.l9l,l76 and in a documententitled Technical Memorandum- Program Requirements for 2 MinuteIntegrated Doppler Satellite Navigation Solution" edited by .l. B.Moffctt and identified as document No. TG 8I9-I(Rev.). published inSept. I971. by the Johns Hopkins University Applied Physics Laboratoryin Silver Spring. Md.

A suitable tape reader for performing the function of the tape reader Tof readingin the program controlling operation of the computer C is aChalco highspecd paper tape photo reader. for example.

CONTROL PANEL. DISPLAY AND CONTROL KEYBOARD Considering the display D indetail. (FIG. 5) a group of address gates I90 respond to signals fromthe computer C transferring information between the computer C and aplurality of storage registers I92. The information stored in thestorage registers I92 is provided to a plurality of decoder drivers I94which provide output signals to drive the display lamps (I-IG. 3)mounted on the display panel P. The address gates I90 further receive.in addition to the signals encrgiling the storage registers I92. signalsfrom a conductor I96 to receive information from a set of storageregisters 198 in the control keyboard K (FIG. 6). The storage registers198 receive and store information in the form of requests provided by aset ofencodcrs 200 which respond to operation of the keys on the controlkeyboard K (FIGS. 4 and 6).

Considering the control keyboard K more in detail. this keyboard ismounted with the control panel P bebind a folding door so that thecontrol keyboard K may be moved inwardly and enclosed within the controlpanel P preventing inadvertent operation of one of the control keyswhich could interfere with or destroy the successful processing of thedata by the computer C uring that cycle. The control keyboard includeswenty-four keys. ten of which. as indicated by refernce numeral 202 areassigned to the ten Arabic nu ierals I. 2. 3. 4. 5. 6. 7. 8. 9 and t). Akey 203 is asigned to a decimal point and permits the operator of heapparatus A to insert a decimal point in the proper lace in the data hedesires to enter into the computer. key 204 is assigned to an algebraicminus sign. persitting the user of the apparatus A to enter negative.ata when it is desirable or necessary to do so. A conrol key 206labeled ENT. controls the keyboard K and iotifics the computer C throughthe circuit of the dis ilay D (FIG. that the user of the apparatus Adesires 0 enter data into the computer C and permits the comiuter C torespond and accept such data in the form of iumerical informationentered by means of the numeri- :al keys 202. The remaining control keyson the conrol keyboard K permit the user of the apparatus A to :nterand/or display certain of the control functions icing processed by thecomputer C.

An AUX key 208 allows for special function entry nto the computer Cand/or display by the display neans D by depressing the key 208 forauxiliary, plus I secondary control key of the type set forth below.)ermitting entry of secondary data and/or information ind displaythereof.

An AUTO key 2l0 causes the computer C to perorm automatic. sequentialdisplay on the display D of atitude. longitude and Greenwich Mean Time.each of .he three parameters being displayed for consecutive 6 iecondintervals. An GMT key 212 allows for entry into .he computer C and/ordisplay on the display D of Greenwich Mean Time. An HDG key 214 allowsfor :ntry into the computer C and/or display on the display D of theheading of the users vehicle. An SPD key 218 .lllOWS for entry into thecomputer C and/or display on the display D of the speed or velocity ofthe user's vehi- :lc.

An LAT key 220 allows for entry into the computer C and/or display onthe display D of the latitude of the user's vehicle.

An XTK key 222 allows for display on the display D of the cross-trackdistance relative to either a previously defined Great Circle or rhumbline course.

An WPT key 224 allows the operator of the appara- [us A to enter thelatitude and longitude of a waypoint towards which the vehicle of theuser is to steer. The WPT key 224 must be used in conjunction with theLAT key 220 to enter latitude and in conjunction with a LON key 226 toenter longitude. The LON key 226 allows for entry into the computer Cand/or display on the display D of the longitude of the user's vehicle.

An LFX key 228 allows the operator ofthe apparatus A to request thecomputer C to display on the display D sequentially the latitude,longitude and GMT or Greenwich Mean Time of the last satellite positionfix performed by the computer C.

An ANT key 230 allows the operator of the apparatus A to enter into thecomputer C and/or display on the display D of the height of thesatellite signal receiving antenna N above or below the reference geoid.

The display lamps of the display D mounted on the display panel P (FIG.3) contain eight data windows 232. A first data window 233 is used onlyfor certain data displays and can indicate l. *l or as controlled by thecomputer C. The remaining data display win dows 232 can indicate anyArabic numeral requested or computed, with provision for illuminateddecimal points at certain windows indicated at 233a.

The panel p also contains twelve function display windows 234. Thosefunction display windows 234 bearing like code indicators on their faceto the code indicators on the keyboard K indicate that such key has beendepressed and a request for entry or display of such data has been madeby the user and that such data is being displayed in the data windows232. A plot function indicator window 236 is provided to indicated.should it be desirable to use the computer C in conjunction with theplotter. that a request has been made by the plotter to be initializedby data in the computer C. Such data requested by the plotter would bealso displayed on the display D.

An alarm indicator lamp 238 of the function display windows 234 whenflashing periodically indicates that there has been a power failure inthe power supply to the computer C. but that the computer C hassubsequently received power and started operations once more and thataccordingly the data in the computer C. such as the Greenwich Mean Time.may no longer be valid, alerting the operator to request a display ofthis data and so determine. The alarm indicator window 238 isadditionally continuously energized in the case that the computer C hasnot requested the clock interrupt circuit 168 of the interface circuit lto provide the one hundred millisecond clock pulse for four consecutiveclock pulse intervals. This circuitry is conventional and could includea resettable "TIMES 4 counter which is reset at each request for a clockpulse from the computer C but which energizes the alarm lamp 238 in casea count of four is reached. Failure of the computer C to request a clockpulse for this 400 millisecond interval would indicate that the computerC is locked in a sub-routine and a program failure has occurred,alerting the operator of the apparatus A.

Considering now the remainder of the control panel P (FIGS. 2 and 3). asynchronization indicator light 240 on the control panel P is energizedby the message synchronization counter Z in the receiver circuit R overthe conductor when the synchronization code is received from thesatellite. The indicator lamp 240 is manually depressible as indicatedby the switch 242 permitting a manual override and rejection of anyincoming message which the user does not wish to pro cess. Anacquisition indicator light 244 is energized by a suitable switch. suchas a transistor or relay upon reeeipt of the indication of a phase lockfrom the output terminal 40 connected to the indicator 32 and the phaselock loop. Energization of the acquisition indica tor light 244indicates that the output frequency signal from the satellite and thelocal reference frequency signal have been synchronized in the phaselock loop M. The acquisition indicator lamp 244 is further manuallydepressible in order to reject acquisition of a satellite signalmanually. should the operator decide to do so.

An ON indicator lamp 248 is energized and indicates on the panel P thatthe apparatus A, as indicated by a switch 250, has been connected to asuitable alternating current power supply to energize the apparatus A.

A frequency meter 252 is electrically connected to the conductor 72 toprovide an indication of the doppler frequency output from the dopplerdemodulator X (FlG. 7B). The indicia on the face of the meter 252 are toindicate kilohcrtz. since the normal range oi'the dopplcr frequency ofan orbiting satellite is in the range of from kilohertz to 44 kilohertz.as is known.

Additionally. it is sometimes desirable that an aural indication of theabsence of phase lock be provided. In this situation. a loudspeaker orother suitable electric to audible transducer is provided andelectrically connected to the conductor 50 which provides a relativelylow or zero output when phase lock is obtained, and noise at othertimes. In these situations, it is sometimes desirable for a volumecontrol to be introduced in the circuit of the speaker to reduce noisedistraction. In these embodiments. a volume control potentiometer 254 iselectrically connected to the conductor 50 between the output of thephase detector Q and the speaker. permitting the operator of theapparatus A to vary the signal level out of the speaker by adjusting aknob 256 on the display panel P.

It is also preferable that an autosweep circuit be included in thereceiver R to cause the receiver R to scan the frequency spectrum oftheincoming satellite signal in the event no satellite signal has beenacquired. In certain situations, it may be desirable to disregard thesignal from a satellite recently acquired and tune for a secondsatellite signal of greater interest. In these situations. theacquisition button 246 is depressed by the user. causing rejection ofthe signal acquired, and electrically connecting a tuning potentiometer258 to the receiver R permitting manual sweep of the frequency spectrumexpected for the desired incoming signal. A control knob 260 on thepanel permits the user of the apparatus A to perform this tuningoperation.

A light dimming circuit 262 with the control panel P (FIG. 2) respondsto movement of a control knob 264 on the control panel P andelectrically connects a diode bridge 266 of parallel connected diodesand a serially connected diode bridge of parallel connected diodes 268into the energizing circuit of the lamps of the apparatus A in responseto movement of the control knob 264. Movement of the control knob 264accordingly selectively varies the illumination intensity of the lampsallowing the user of the apparatus A to dim these lamps when he desiresto do so.

A lamp test push button 270 (FIGS. 2 and 3). permits the user of theapparatus A to press the button 270 and determine whether the seveencomplete integer data display lamps 232 on the display panel P areoperable. If such lamps are operable, depression of the button 270causes the display lamps to indicate their operability by forming adisplay of the integer 8. Depression of the lamp test button 270 furtherpermits the operator of the apparatus A to control the alarm light 238in the display panel P. If the alarm light 238 is flashing. indicating apower failure in the manner set forth above, depression of the pushbutton 270 turns this light off. However. in the event that the alarmlight 238 is not blinking but continuously energized. a program failureofthe type set forth above is indicated and the program must be reloadedinto the computer C from the tape reader T.

The control panel P (FIG. 2) further includes two control switches. onea stop switch 272 permitting the user of the apparatus A to cause anemergency stop of the computer C should it become necessary to do so. Aload switch 274 causes the computer C to request the tape reader T tobegin to read in the program controlling the operation of the computer Cfrom the tape so that operations of the apparatus A may begin.

OPERATION OF INVENTION In the operation of the apparatus A. the receiverR responds to the signal sent from the satellite in the form ofa fixedfrequency signal containing the phase modu lated pulse doublets of orbitdefinition data and the intermediate frequency circuit F demodulates thefixed frequency signal for processing and furnishes the demodulatedsignal to the phase detector O to determine the phase of the demodulatedsignal from the intermediate frequency circuit F. The phase lock loopmeans M receives an output ofthe phase detector 0 and regulates thefrequency of the intermediate frequency circuit F. The local oscillator0 forms a reference fre quency signal which is furnished to thesynthesizer S in order to form demodulating frequency signals for theintermediate frequency circuit F. the phase detector Q. and the dopplerdemodulator X. which responds to an output from the phase loop means Mand the demodu lating frequency signal from the synthesizer S todetermine the dopplcr shift in the frequency of the signal sent from thesatellite. The doppler shift in the frequency due to the movement of thesatellite with rcspect to the vehicle with which the apparatus A ismounted may be monitored on the frequency meter 252 of the display panelP.

The bit phase detector B determines the phase of the orbit definitiondata pulse doublets and provides an output signal to the bit rate phaselock loop means L in order to control the phase of the orbit definitiondata pulse doublets. The orbit definition data from the phase modulatedpulse doublets is decoded in the data decoder Y and provided. along withthe doppler shift. to the computer C which processes such data in orderto determine the location of the vehicle.

The interface circuit l provides the doppler shift and orbit definitiondata to the computer. having counted the doppler shift in the dopplercounter 174 therein before finishing such signals to the computer C.

After processing. the display means D can then indi cate the location ofthe vehicle determined by the com puter C so that the user of theapparatus A may precisely and accurately locate himself and the vehiclewith which the apparatus A is mounted on the earth.

Although the apparatus A has been set forth in the preferred embodimentas used in conjunction with the Transit Satellite. it should beunderstood that the apparatus A is suitable for use with other types ofsatellites sending doppler shift and orbit definition data. as well.Also. when it is desirable for ionospheric refraction correctionpurposes to receive the ISO megahertz signal sent by the TransitSatellite. the apparatus A can be readily adapted for such purposes byaddition of another receiver R having an IF section F tuned to therequisite frequencies for ISO megahertz reception. and addition of asecond interface circuit I having a doppler counter circuit I74 thereinto provide a doppler count of the second frequency channel sent by thesatellite.

The foregoing disclosure and description of the invention areillustrative and explanatory thereof. and various changes in the size.shape. materials. wiring connections and contacts as well as in thedetails of the illustrated circuitry and construction may be madewithout departing from the spirit of the invention.

We claim:

I. An apparatus for processing data. sent from a satellite in the formof a fixed frequency signal containing transmits a synchronizationpattern code before sending the orbit data definition hits. and whereinsaid rephase modulated pulse doublets or orbit definition data. todetermine a position of a vehicle on the earth. comprising: eeiver meansfurther comprises;

a. receiver means for receiving the signal from the messagesynchroni/ation counter means for detectsatellite; said receiver meanscomprising: 5 ing the synchronization pattern code and indicating 1.intermediate frequency means for domodulating receipt of same.

the fi ted frequency signal for processing; 3. The structure of claim I.further including:

2. phase detector means for determining the phase tape reader means forreading an operation controlof the demodulated signal from saidintermediate ling program into said computer means. frequency means; it)4. The structure of claim I. wherein said receiver 3. phase lock loopmeans receiving an output of means further includes;

said phase detector means for regulating the frcgain control means forlimiting the gain of said interquency of said intermediate frequencymeans; mediate frequency means.

4. doppler demodulator means responsive to an 5. The structure of claimI. wherein said interface output of said phase lock loop means for deter5 circuit means further includes: mining the doppler shift in frequencyof the sig' data multiplexer means for multiplexing the decoded nal sentfrom the satellite; orbit description data and the doppler count from 5.local oscillator means for forming a reference said doppler countermeans for processing by said frequency signal; computer means.

6. synthesi/ermeans for forming demodulating fre- 3t) 6. The structureof claim I. wherein the satellite queney signals for said intermediatefrequency sends messages of orbit definition data at repeated timemeans. said phase detector means and said dop intervals. and whereinsaid interface circuit means inpler demodulator means from saidreference freeludes:

quency signal;

7. hit phase detector means for determining the phase of the orbitdefinition data phase doublets;

8. hit rate phase lock loop means for controlling the phase of the orbitdefinition data pulse doublets; and

9. data decoder means for decoding the orbit definition data from thephase modulated pulse doublets;

b. computer means for processing the doppler shift and orbit definitiondata to determine the location of the vehicle.

c. interface circuit means for providing the doppler shift and orbitdefinition data to said computer means. said interface circuit meansincluding doppler counter means for counting the doppler shift;

interrupt means for notifying said computer means of receipt of a newmessage of orbit definition data. 7. The structure of claim 6, whereinsaid interface circuit means comprises:

means includes:

error detection means for detecting errors in the data received from thesatellite. 9. The structure of claim 8, wherein said receiver meansincludes:

counter means for counting a predetermined number of valid data beforetransmitting such data to said computer means.

and 40 [0. The structure of claim 1, further including: d. display meansfor indicating the location of the vemeans for entry of data andrequests therefor into hicle determined by said computer means. saidcomputer means. 2. The structure of claim 1, wherein the satellite

1. An apparatus for processing data, sent from a satellite in the formof a fixed frequency signal containing phase modulated pulse doublets ororbit definition data, to determine a position of a vehicle on theearth, comprising: a. receiver means for receiving the signal from thesatellite, said receiver means comprising:
 1. intermediate frequencymeans for domodulating the fixed frequency signal for processing; 2.phase detector means for determining the phase of the demodulated signalfrom said intermediate frequency means;
 3. phase lock loop meansreceiving an output of said phase detector means for regulating thefrequency of said intermediate frequency means;
 4. doppler demodulatormeans responsive to an output of said phase lock loop means fordetermining the doppler shift in frequency of the signal sent from thesatellite;
 5. local oscillator means for forming a reference frequencysignal;
 6. synthesizer means for forming demodulating frequency signalsfor said intermediate frequency means, said phase detector means, andsaid doppler demodulator means from said reference frequency signal; 7.bit phase detector means for determining the phase of the orbitdefinition data phase doublets;
 8. bit rate phase lock loop means forcontrOlling the phase of the orbit definition data pulse doublets; and9. data decoder means for decoding the orbit definition data from thephase modulated pulse doublets; b. computer means for processing thedoppler shift and orbit definition data to determine the location of thevehicle; c. interface circuit means for providing the doppler shift andorbit definition data to said computer means, said interface circuitmeans including doppler counter means for counting the doppler shift;and d. display means for indicating the location of the vehicledetermined by said computer means.
 2. The structure of claim 1, whereinthe satellite transmits a synchronization pattern code before sendingthe orbit data definition bits, and wherein said receiver means furthercomprises: message synchronization counter means for detecting thesynchronization pattern code and indicating receipt of same.
 2. phasedetector means for determining the phase of the demodulated signal fromsaid intermediate frequency means;
 3. phase lock loop means receiving anoutput of said phase detector means for regulating the frequency of saidintermediate frequency means;
 3. The structure of claim 1, furtherincluding: tape reader means for reading an operation controllingprogram into said computer means.
 4. The structure of claim 1, whereinsaid receiver means further includes: gain control means for limitingthe gain of said intermediate frequency means.
 4. doppler demodulatormeans responsive to an output of said phase lock loop means fordetermining the doppler shift in frequency of the signal sent from thesatellite;
 5. local oscillator means for forming a reference frequencysignal;
 5. The structure of claim 1, wherein said interface circuitmeans further includes: data multiplexer means for multiplexing thedecoded orbit description data and the doppler count from said dopplercounter means for processing by said computer means.
 6. The structure ofclaim 1, wherein the satellite sends messages of orbit definition dataat repeated time intervals, and wherein said interface circuit meansincludes: interrupt means for notifying said computer means of receiptof a new message of orbit definition data.
 6. synthesizer means forforming demodulating frequency signals for said intermediate frequencymeans, said phase detector means, and said doppler demodulator meansfrom said reference frequency signal;
 7. bit phase detector means fordetermining the phase of the orbit definition data phase doublets; 7.The structure of claim 6, wherein said interface circuit meanscomprises: message reject means for suppressing output signals from saiddata decoder means in response to a message reject signal from saidcomputer means.
 8. The structure of claim 1, wherein said receiver meansincludes: error detection means for detecting errors in the datareceived from the satellite.
 8. bit rate phase lock loop means forcontrOlling the phase of the orbit definition data pulse doublets; and9. data decoder means for decoding the orbit definition data from thephase modulated pulse doublets; b. computer means for processing thedoppler shift and orbit definition data to determine the location of thevehicle; c. interface circuit means for providing the doppler shift andorbit definition data to said computer means, said interface circuitmeans including doppler counter means for counting the doppler shift;and d. display means for indicating the location of the vehicledetermined by said computer means.
 9. The structure of claim 8, whereinsaid receiver means includes: counter means for counting a predeterminednumber of valid data before transmitting such data to said computermeans.
 10. The structure of claim 1, further including: means for entryof data and requests therefor into said computer means.